1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to fabricating cell plugs of a semiconductor device, which reduces cell plug resistance and thereby increases the reading/writing operation speed of the semiconductor device.
2. Discussion of the Related Art
A method for fabricating cell plugs of a semiconductor device according to a related art will be described with reference to the accompanying drawings. Particularly, FIGS. 1A to 1G are sectional views illustrating process steps for fabricating cell plugs of a Metal-Insulator-Metal (MIM) Structure according to a related art.
As shown in FIG. 1A, a plurality of gates 12 are formed on a predetermined region of a semiconductor substrate 11. An insulating film is deposited on the entire surface of the semiconductor substrate 11 including the gates 12. The insulating film is then selectively removed to form insulating film sidewalls 13 on both sides of the gates 12.
Then, although not shown, impurity ions are injected into a predetermined region of the semiconductor substrate 11 so as to form source/drain impurity regions in the semiconductor substrate 11 at both sides of the gates 12 adjacent the insulating film sidewalls 13.
Afterwards, a first insulating interlayer 14 of a predetermined thickness is deposited on the entire surface of the semiconductor substrate 11. The first insulating interlayer 14 is then polished by an etch-back or chemical mechanical polishing (CMP) process to expose upper portions of the gates 12.
Then, the first insulating interlayer 14 is selectively removed so that a portion above the semiconductor substrate 11 corresponding the source/drain impurity region between the gates 12 is exposed to define a first contact hole 17a through the first insulating interlayer 14. A polysilicon or monosilicon film is buried in the first contact hole 17a to form a first cell plug 15.
Subsequently, a second insulating interlayer 16 is deposited on the entire surface of the semiconductor substrate 11 and selectively removed by photolithography or etching processes. This exposes an upper surface of the first cell plug 15 and its adjacent regions to define a second contact hole 17b through the second insulating interlayer 16.
Then, as shown in FIG. 1B, a second cell plug material 18 is deposited on the entire surface of the semiconductor substrate 11 including the second contact hole 17b. In this case, a monosilicon or polysilicon film is used as the second cell plug material 18.
Then, as shown in FIG. 1C, the second cell plug material 18 on an upper portion of the second insulating interlayer 16 is selectively removed to remain only in the second contact hole 17b. This forms a second cell plug 18a. In this case, the second cell plug material 18 is removed by an etch-back or CMP process.
Then, as known, a silicide contact as well as a barrier metal are formed between a storage node and the second cell plug 18a to produce a MIM structure. In this process, to define regions for forming the silicide contact and the barrier metal, as shown in FIG. 1D, the upper portion of the second cell plug 18a is removed by a thickness of several tens of nm by an etch-back process. Then, as shown in FIG. 1E, a silicide contact 19 made of a titanium silicide film is formed on the exposed upper surface of the second cell plug 18a. This can be accomplished by depositing a titanium film using a physical vapor deposition (PVD) process, annealing the titanium film to cause silicon in the second cell plug 18a to react with the titanium in the titanium film, and removing portions of the titanium film that do not react with silicon. In the alternative, the silicide contact 19 can be formed by using an in-situ titanium silicide deposition process through a chemical vapor deposition (CVD) process.
Then, as shown in FIG. 1F, a titanium nitride film 20 is deposited on the entire surface of the semiconductor substrate 11 including the silicide contact 19. Subsequently, as shown in FIG. 1G, the titanium nitride film 20 on the upper portion of the second insulating interlayer 16 is selectively removed by an etch-back or CMP process so as to form a barrier film 20a on the silicide contact 19. Then, a MIM capacitor (not shown) is formed, which comes into contact with the barrier film 20a. This completes the method of fabricating the cell plugs of a semiconductor device having a MIM structure according to the related art.
These are, however, at least several problems that are associated with such conventional methods. First, silicon of high specific resistance is used as cell plug materials for the first and second cell plugs 15 and 18a. This increases the cell plug resistance of the semiconductor device (e.g., memory device) in accordance with the design rules of the semiconductor device. An increase in the cell plug resistance is a problem because it decreases the reading/writing operation speed of the semiconductor device.
Second, in order to form the silicide contact 19 and the barrier film 20a between a lower electrode of the MIM capacitor and the second cell plug 18a, the conventional method requires complicated processes such as an etch-back process for forming the second cell plug 18a, processing steps including a polishing process for forming the barrier film 20a, etc. As a result, the conventional method of fabricating cell plugs involves complex and multiple steps and requires lengthy processing time.